View KM68257C-12_494870.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KM68257C/CL
Document Title
PRELIMINARY CMOS SRAM
32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial Temperature Range.
Revision History
Rev No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to final Data Sheet. 1. Delete Preliminary Update A.C parameters 2.1. Updated A.C parameters Previous spec. Updated spec. Items (12/15/20ns part) (12/15/20ns part) tOE - / 8/10ns - / 7 /9 ns tCW - /12/ - ns - /11/ - ns tHZ 8/10/10ns 6/7/8ns tOHZ - / 8 / - ns - / 7 / - ns tDW - / 9 / - ns - / 8 / - ns 2.2. Add Voh1=3.95V with the test condition as Vcc=5V5% at 25C 3.1. Add 28-TSOP1 Package. 3.2. Add L-version. 3.3. Add Data Rentention Characteristics. Draft Data Apr. 1st, 1994 May 14th,1994 Remark Preliminary Final
Rev. 2.0
Oct. 4th, 1994
Final
Rev. 3.0
Feb. 22th, 1996
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1Rev 3.0 February-1996
KM68257C/CL
32K x 8 Bit High-Speed CMOS Static RAM
FEATURES
U U
PRELIMINARY CMOS SRAM
GENERAL DESCRIPTION
The KM68257C is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The KM68257C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG's advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM68257C is packaged in a 300 mil 28-pin plastic DIP, SOJ or TSOP1 forward.
U
U
U
U
U
U
U
Fast Access Time 12, 15, 20A(Max.) Low Power Dissipation Standby (TTL) : 40I(Max.) (CMOS) : 2I(Max.) 0.1I(Max.)- L-ver. only Operating KM68257C/CL - 12 : 165I(Max.) KM68257C/CL - 15 : 150I(Max.) KM68257C/CL - 20 : 140I(Max.) Single 5.0V10% Power Supply TTL Compatible Inputs and Outputs I/O Compatible with 3.3V Device Fully Static Operation - No Clock or Refresh required Three State Outputs Low Data Retention Voltage : 2V(Min.)- L-ver. only Standard Pin Configuration KM68257C/CLP : 28-DIP-300 KM68257C/CLJ : 28-SOJ-300 KM68257C/CLTG : 28-TSOP1-0813, 4F
PIN CONFIGURATION(Top View)
OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2
TSOP1
FUNCTIONAL BLOCK DIAGRAM
Clk Gen. A3 A4 A5 A6 A7 A8 A12 A13 A14 I/O1 ~ I/O8 Pre-Charge-Circuit
A14 1 A12 2
28 Vcc 27 WE 26 A13 25 A8 24 A9 23 A11
Row Select
A7 3
Memory Array 512 Rows 64x8 Columns
A6 4 A5 5 A4 6 A3 7 A2 8 A1 9
SOJ/DIP
22 OE 21 A10 20 CS 19 I/O8 18 I/O7 17 I/O6 16 I/O5 15 I/O4
Data Cont.
I/O Circuit Column Select
A0 10 I/O1 11 I/O2 12
CLK Gen. A0 CS WE OE A1 A2 A9 A10 A11
I/O3 13 Vss 14
PIN FUNCTION
Pin Name A0 - A14 WE CS OE I/O1 ~ I/O8 VCC VSS -2Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground Rev 3.0 February-1996 Pin Function Address Inputs
KM68257C/CL
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70
PRELIMINARY CMOS SRAM
Unit V V
W
C C
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and functional operation of the device at these at these or any other conditions above those indicated in the operating sections of thi s specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70C)
Parameter Supply Voltage Ground Input Low Voltage Input Low Voltage
* VIL(Min) = -2.0(Pulse Width 10ns) for I20I ** VIH(Max) = VCC+2.0V(Pulse Width 10ns) for I20I
Symbol VCC VSS VIH VIL
Min 4.5 0 2.2 -0.5*
Typ 5.0 0 -
Max 5.5 0 VCC+0.5** 0.8
Unit V V V V
DC AND OPERATING CHARACTERISTICS(TA=0 to 70C,VCC=5.0V10% unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Symbol ILI ILO Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=0.1mA Normal L-ver 12ns 15ns 20ns Min -2 -2 2.4 Max 2 2 165 150 140 40 2 0.1 0.4 3.95 Unit A A
Operating Current
ICC ISB
I I I
V V V
Standby Current Output Low Voltage Level Output High Voltage Level
* VCC=5.0V5% Temp.=25C
ISB1 VOL VOH VOH1*
CAPACITANCE*(TA =25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN Max 8 7 Unit pF pF
* NOTE : Capacitance is sampled and not 100% tested.
-3-
Rev 3.0 February-1996
KM68257C/CL
AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.)
TEST CONDITIONS
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads Value 0V to 3V 3A 1.5V See below
PRELIMINARY CMOS SRAM
Output Loads(A) +5V 480 DOUT 255 30pF*
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V 480 DOUT 255 5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Access Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD KM68257C/CL-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 6 12 KM68257C/CL-15 Min 15 3 0 0 0 3 0 Max 15 15 7 7 7 15 KM68257C/CL-20 Min 20 3 0 0 0 3 0 Max 20 20 9 10 10 20 Unit
A A A A A A A A A A A
-4-
Rev 3.0 February-1996
KM68257C/CL
WRITE CYCLE
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW KM68257C/CL-12 Min 12 9 0 9 9 12 0 0 7 0 0 Max 6 KM68257C/CL-15 Min 15 11 0 12 12 15 0 0 8 0 0 Max 8 -
PRELIMINARY CMOS SRAM
KM68257C/CL-20 Min 20 13 0 13 13 20 0 0 10 0 0 Max 8 Unit
A A A A A A A A A A A
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC ADD tAA tOH Data Out Previous Data Valid Data Valid
-5-
Rev 3.0 February-1996
KM68257C/CL
TIMING WAVE FORM OF READ CYCLE(2) (WE=VIH)
tRC ADD tAA tCO CS tOE OE tOLZ tLZ(4,5) Data Out Vcc Current
NOTES(READ CYCLE)
PRELIMINARY CMOS SRAM
tHZ(3,4,5)
tOHZ
tOH Data Valid
Icc ISB
tPU 50%
tPD 50%
1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels. 4. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ (Min.) both for a given device and from device to device. 5. Transition is measured 200AE from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
TIMING WAVE FORM OF WRITE CYCLE(1) (OE=Clock)
tWC ADD tAW OE tCW(3) CS tAS(4) WE tDW Data In High-Z tOHZ(6) High-Z(8) Data Out Data Valid tDH tWP(2) tWR(5)
-6-
Rev 3.0 February-1996
KM68257C/CL
TIMING WAVE FORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC ADD tAW tCW(3) CS tAS(4) WE tDW Data In High-Z tWHZ(6) Data Valid tWP1(2)
PRELIMINARY CMOS SRAM
tWR(5)
tOH
tDH
tOW Data Out High-Z(8)
(10)
(9)
TIMING WAVE FORM OF WRITE CYCLE(3) (CS=Controlled)
tWC ADD tAW tCW(3) CS tAS(4) WE tDW Data In High-Z tLZ Data Out High-Z tWHZ(6) High-Z(8) Data Valid tDH High-Z tWP(2) tWR(5)
-7-
Rev 3.0 February-1996
KM68257C/CL
NOTES(WRITE CYCLE)
PRELIMINARY CMOS SRAM
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS H L L L WE X H H L OE X* H L X Mode Not Select Output Disable Read Write I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC
* NOTE : X means Don't Care.
DATA RETENTION CHARACTERISTICS*(TA = 0 to 70C)
Parameter VCC for Data Retention Data Retention Current Data Retention Set-Up Time Recovery Time
* L-Ver only.
Symbol VDR IDR tSDR tRDR
Test Condition CSVCC - 0.2V VCC = 3.0V, CSVCC - 0.2V VINVCC - 0.2V or VIN0.2V See Data Retention Wave form(below)
Min. 2.0 0 5
Typ. -
Max. 5.5 0.07 -
Unit V
I
ns ms
DATA RETENTION WAVE FORM(CS Controlled)
tSDR Data Retention Mode tRDR
VCC 4.5V
2.2V
VDR CSVCC - 0.2V CS GND
-8-
Rev 3.0 February-1996
KM68257C/CL
PACKAGE DIMENSIONS
28-DIP-300
PRELIMINARY CMOS SRAM
Units : Inches (millimeters)
+0.10 -0.05 +0.004 0.010 -0.002
0.25
#28
#15
7.010.20 0.2760.008
#1
#14
7.62 0.300
0~15E
34.69 1.366MAX 34.290.20 1.3500.008
3.810.20 0.1500.008 5.08 0.200MAX
(
0.65 ) 0.025
0.460.10 0.0180.004 1.270.10 0.0500.004
3.18 2.54 0.100 0.51 MIN 0.020
+0.30 -0.25 0.125+0.012 -0.010
28-SOJ-300
#28 #15
8.510.12 0.3350.005
7.62 0.300
6.860.25 0.2700.010 0.20
+0.10 -0.05
0.008+0.004 -0.002
#1
#14 0.69 MIN 0.027 18.82 MAX 0.741 18.410.12 0.7250.005 ( 1.30 ) 0.051
3.76 MAX 0.148 0.10 0.004MAX 0.43 ( 0.95 ) 0.0375
+0.10 -0.05
0.017+0.004 -0.002
1.27 0.050
+0.10 -0.05 +0.004 0.028 -0.002
0.71
(
1.30 ) 0.051
-9-
Rev 3.0 February-1996
KM68257C/CL
PACKAGE DIMENSIONS
28-TSOP1-0813.4F
PRELIMINARY CMOS SRAM
Units : Inches (millimeters)
1.10 MAX 0.004 MAX
0.20
+0.10 -0.05 0.008+0.004 -0.002
13.400.20 0.5280.008 #28 ( 8.40 0.331 MAX 8.00 0.315 0.425 ) 0.017
#1
0.55 0.0217
#14 0.25 0.010 TYP
#15 1.000.10 0.0390.004 1.20 0.047 MAX 0.05 0.002 MIN
11.800.10 0.4650.004
+0.10 -0.05 0.006+0.004 -0.002
0.15
0~8E
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
- 10
Rev 3.0 February-1996

▲Up To Search▲

Price & Availability of KM68257C-12

	To Download KM68257C-12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .